1. Field
This invention relates generally to a field effect transistor (FET) device including an etch stop layer that defines the etch depth of a gate terminal recess and, more particularly, to an FET device including an etch stop layer that defines the etch depth of a gate terminal recess, where the etch stop layer is an undoped GaAs layer deposited on an AlGaAs barrier layer.
2. Discussion
Field effect transistors (FET) are well known in the transistor art, come in a variety of types, such a HEMT, MOSFET, MISFET, FinFET, etc., and can be integrated as horizontal devices or vertical devices. A typical FET will include various semiconductor layers, such as silicon, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium nitride (GaN), indium phosphide (InP), etc. Sometimes the semiconductor layers are doped with various impurities, such as boron or silicon, to increase the population of carriers in the layer, where the higher the doping level of the layer the greater the conductivity of the particular semiconductor material. An FET will also include a source terminal, a drain terminal and a gate terminal, where one or more of the semiconductor layers is a channel layer and is in electrical contact with the source and drain terminals. An electrical potential provided to the source terminal allows electrical carriers, either N-type or P-type, to flow through the channel layer to the drain terminal. An electric signal applied to the gate terminal creates an electrical field that modulates the carriers in the channel layer, where a small change in the gate voltage can cause a large variation in the population of carriers in the channel layer to change the current flow from the source terminal to the drain terminal.
Integrated circuits are typically fabricated by epitaxial fabrication processes that deposit or grow the various semiconductor layers on a semiconductor substrate to provide the circuit components of the device. Substrates for integrated circuits include various semiconductor materials, such as silicon, InP, GaAs, SiC, etc. As integrated circuit fabrication techniques advance and become more complex, more circuit components are able to be fabricated on the substrate within the same area and be more closely spaced together. Further, these integrated circuit fabrication techniques allow the operating frequencies of the circuit to increase to very high frequencies, well into the GHz range.
In a typical FET device, the source terminal and the drain terminal are usually fabricated on a heavily doped cap layer to provide a better conductive path to the channel layer. For certain FET devices, higher performance can be achieved by forming a recess through the cap layer and fabricating the gate terminal in the recess so that it is closer to the channel layer. By placing the gate terminal closer to the channel layer, the transconductance Gm of the device is improved by providing more effective control of the charge in the channel layer, which provides faster switching times.
A typical GaAs FET device includes a heterojunction structure defined by an N+ GaAs cap layer provided on an AlGaAs Schottkey barrier layer. A gate recess is formed by first depositing a photoresist layer over the cap layer for all of the devices on the wafer that is patterned to define an opening therein through which the gate recess can be etched into the heterojunction structure. A typical gate recess etching process for this type of device generally requires a two-step etching process using two chemical etching solutions, for example, a first etch solution including hydrochloric acid (HCL) and deionized water (DI) and a second etch solution including ammonia (NH4OH) and hydrogen peroxide (H2O2). In one specific example, the two-step etching process includes an initial HCL:DI oxide etch, a deionized water rinse without drying, an initial NH4OH:H2O2:DI etch, and then another deionized water. This two-step etching process is repeated over 10-16 cycles to reach the desired depth of the gate recess into the AlGaAs barrier layer.
The gate recess etching process discussed above has a number of drawbacks. For example, the number of two-step etching cycles required makes the process labor intensive and more costly. Further, because of the limitations of the process, the depth of the gate recess etch for a particular FET device on the wafer may not be optimal, and may be different than other gate recess etches of other FET devices on the same wafer, which affects device non-uniformity and performance.